1. Field of the Invention
The present invention relates to a semiconductor memory, and more specifically to a semiconductor memory including a plurality memory blocks each having a plurality of input/output circuits, and an active circuit area containing different kinds of circuit blocks and located between the input/output circuits of the memory blocks.
2. Description of Related Art
In a semiconductor memory including a plurality memory blocks each having a plurality of input/output circuits in order to receive and output, in parallel, a plurality of bits of writing and reading multi-bit data (simply called "data" or "input/output data" hereinafter) for one or a plurality of memory plates, it is a general practice to locate, between the plurality memory blocks, an active circuit area containing a plurality of circuit blocks for executing a block designation control, an address designation control and a data input/output control for the plurality of memory blocks, in such a manner that the plurality memory blocks are in symmetry to the axis of the active circuit area.
One prior art example of this type semiconductor memory is shown in FIG. 4.
The shown semiconductor memory includes four memory blocks MB1 to MB2 each including four input/output circuits (one set of IO11-IO14, IO21-IO24, IO31-IO34, IO41-IO44) for a parallel inputting/outputting of a 4-bit data for one memory plate (one of MP1 to MP4) (or a plurality of memory plates or which may be divided into a plurality), an active circuit area ACA containing a plurality of circuit blocks CB for executing a block designation control, an address designation control and a data input/output control for the memory blocks MB1 to MB4, and read/write bus lines RWB11 to RWB14 and RWB21 to RWB24 for transferring the input/output data for the memory blocks MB1 to MB4 and also transferring the input/output data through predetermined input/output electrodes (not shown) to an external circuit. The memory blocks are located to locate therebetween the active circuit area ACA in such a manner that the memory blocks MB1 and MB2 are located at one side of the active circuit area ACA and the memory blocks MB3 and MB4 are located at the other side of the active circuit area ACA. Between the memory blocks MB1 and MB2 and the active circuit area ACA, the read/write bus lines RWB11 to RWB14 are located which interconnect between mutually corresponding input/output circuits of the memory blocks MB1 and MB2. Between the memory blocks MB3 and MB4 and the active circuit area ACA, the read/write bus lines RWB21 to RWB24 are located which interconnect between mutually corresponding input/output circuits of the memory blocks MB3 and MB4.
In addition, the input/output data for the mutually corresponding input/output circuits of the memory blocks MB1 to MB4, for example, the input/output data for the input/output circuits IO11, IO21, IO31 and IO41, is transferred from and to an external circuit through the read/write bus lines RWB11 and RWB21 and through one input/output electrode provided for example at a predetermined location in the active circuit area ACA. In other words, assuming that the numbers of No. 1 to No. 4 are allocated to the four bits of the parallel four-bit input/output data, the data inputted and outputted through the mutually corresponding input/output circuits of the memory blocks MB1 to MB4, is the data bit allocated with the same number, of the parallel four-bit input/output data.
In this semiconductor memory, if the numbers of No. 1 to No. 4 are allocated in order from one end to the other end for input/output circuit locating positions of the input/output circuits of the memory blocks MB1 to MB4 for easiness of design and evaluation, the input/output circuits for receiving and outputting the data bit of the same number are located at the input/output circuit locating positions of the same number, of the memory blocks MB1 to MB4 (namely, the input/output circuits IO11, IO21, IO31 and IO41 are located at the first input/output circuit locating position). As mentioned above, furthermore, between the active circuit area ACA and the memory blocks MB1 and MB2, the four read/write bus line RWB11 to RWB14 each for transferring the input/output data bit of the same number are located to extend in parallel to each other and connected to the mutually corresponding input/output circuits of the memory blocks MB1 and MB2, respectively. Between the active circuit area ACA and the memory blocks MB3 and MB4, the four read/write bus line RWB21 to RWB24 each for transferring the input/output data bit of the same number are located to extend in parallel to each other and connected to the mutually corresponding input/output circuits of the memory blocks MB3 and MB4, respectively.
In the above mentioned prior art semiconductor memory, the read/write bus lines RWB11 to RWB14 of the same number as the bit number of the parallel input/output data are located in parallel between the active circuit area ACA and the memory blocks MB1 and MB2 and the read/write bus lines RWB21 to RWB24 of the same number as the bit number of parallel input/output data are located in parallel between the active circuit area ACA and the memory blocks MB3 and MB4. In addition, the mutually corresponding bus lines having the same bit position number, of these read/write bus lines are so configured to transfer data to and from an external circuit through the same input/output electrode. Because of this construction, there was a problem that the total length of the read/write bus lines becomes long, and therefore, the parasite capacitance of the read/write bus lines correspondingly increases, with the result that the operation cannot be speeded up. There also was another problem that the region occupied for the read/write bus lines increases, and therefore, the chip area inevitably becomes large.
In this connection, if the read/write bus lines are located at only one side of the active circuit area and connected to corresponding input/output circuits of the memory blocks positioned at the other side of the active circuit area by traversing the active circuit area, the region for the read/write bus lines can be reduced to a half, and the total length of each read/write bus line can be shortened. However, since the circuit block exists at a position where the interconnection for connecting the mutually corresponding input/output circuits is extended to traverse the active circuit area, it is necessary to detour around the circuit block in question, so that the total length of the read/write bus line correspondingly becomes long. In addition, a wiring area for the detour is required at the side opposite to the side where the read/write bus line is located, with the result that the area for the read/write bus line increases.